Why I am not getting chopped negative half wave?

Discussion on both general simulation and Proteus VSM microcontroller simulation.
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jayanthd2k17
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Why I am not getting chopped negative half wave?

Post by jayanthd2k17 »

Why I am not getting chopped negative half-wave?
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Ettore
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Re: Why I am not getting chopped negative half wave?

Post by Ettore »

Because of BR1 bridge.

In order to get max VBUS voltage out you have to set:
1) TD=5m in the GATE generator. When TD=0 the pulses are conincident to zero crossing.
2) V2 in the GATE generator to 3 for IFT greater than 15mA.
3) GATE generator pulse width (PW) to be as short as possible for better stability.
4) Max. SPICE Timestep to 100u for better simulation convergence and stability (System->Set Animation Options)
Kind regards,
Ettore Arena - Labcenter Electronics.
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