Using B inputs to logic analyzer

[louisbertrand]

Hello,
Any hints on using the B0, B1, B2 and B3 inputs to the logic analyzer? The B displays always stay at 00 no matter what I try.
I tried extending the bus stub from the B0 inputs and labelling the counter outputs OUT0 to OUT7. I also tried labelling the wires as a vector (is that even do-able in Proteus?) with OUT[0] to OUT[7].
When I connect the bus wires to the A0 to A2 inputs, I can see the traces just fine.
Proteus 8.11 SP1
Windows 10 Enterprise
Maybe a licence capability issue? Have a look at the Durham College licence.
Test file attached.
Thanks
--Louis

[Ettore]

Licence is not a problem.
The problem is simply that the bus is floating as it has not correctly annotated to net names.
You need to assign a name to the bus and then each net should be annotated consistently to the bus name.
For example you might name the bus OUT[0..7] and annotate the nets connected to with OUT0, OUT1, OUT2...and so on.
How to deal with Busses is described in the Help menu->"Schematic Capture Help" and OBJECT SPECIFIC->Busses chapter.
Find attached the modified schematic showing what I've said above.

[louisbertrand]

Hi Ettore,
Aha! I was not naming the signals and bus correctly. It works fine now.
Grazie,
--Louis

[Ettore]

De rien.