Hidden pin assignments

[understress]

My apologies if this has been covered in the past, I did not find it searching.

Why is it if I place a single logic gate from a chip that would have multiple of the gates, assign the GND and VCC pin nets, the next placed gates do not 'remember' or pick up the setting I made for the first gate? It seems I must go and make the assignments for each gate.

Is this correct? Or can I just make the assignment with the first placed gate and the others work OK? I realize that in the end, the most important part is that I connect the pins correctly in ARES, but I'm a stickler for consistency. I would like all my gates to show the same connections so there is no doubt in the future when someone has to look at prints I've created.

See screen shot of my first placed gate (U3:A) and the start of placing the second gate which shows the hidden pins seemingly connected to different nets.

Suggestions?

Thanks,

Scott

[Paul Spence]

I haven't tried this, but i think if you set up the first gate and then copy it when you need another one, the new one should have the same info in it.

[Iain]

I can also confirm that this will change in Proteus 8 to enforce all gates having the same property set.

Iain.