Odd results using SPICE simulation of 3 phase transformer

[understress]

OK, I've posted a couple of questions regarding this design I'm working on. Now my next.

Attached is the SPICE simulation of my transformer. I am using the V3PHASE to generate the 3 phase primary side voltages for the transformer. Using an analog graph, the input looks like this:

line voltages.JPG (37.29 KiB) Viewed 360 times

But, the output (secondary #1) looks like this:

secondary voltages.JPG (32.28 KiB) Viewed 360 times

I get similar results for secondary #2. Now, at this point I'm assuming I've done something wrong to cause this. But, I can't figure out what it is. I did notice that if I change the time span of the analog graph to 10 seconds, the secondary output looks like this:

secondary voltages 10 sec.JPG (16.58 KiB) Viewed 360 times

So, it seems as if the voltages are trying to 'settle in' towards being centered on zero volts. I've tried having my secondaries connected to earth ground through 100M resistors, as well as having no earth connections to the secondary side. I get the same results either way.

Any help that can be provides is greatly appreciated.

Scott

[understress]

OK, since there is a limit of 3 attachments I thought I would attach the circuit as a reply to my first post. But since I tried to reply so quickly I got a message saying 'You cannot make another post so soon after your last'. Ugh. Then, I waited a few minutes and tried the reply again. Now it says that my file size is too large, and the maximum file size is 256KiB. GRRRR. This is really getting annoying. My zipped design file is 686K. The design file is almost 2 meg. It's a single sheet with some inductors and resistors on it. And 2 analog graphs. I have no clue why the file size is so large.

Anyone have any ideas how I can actually attach my zipped design to this post? Thanks.

Scott

[David]

Hi,

Can you E-mail it to support@labcenter.co.uk. Thanks

Regards,
Dave Spencer.

[Ettore]

Limit for file size and number comes from safety reasons, so we don't intend to change that !

Possibly your graphics contain a lot of data or stop time requires many seconds.
At any rate click right on all the graphics and click 'Clear Graph Data', select Tidy from Edit menu and save the schematic. This reduces as much as possible the file size.

Regarding the envelope problem I suspect this happens because of the configuration of the secondary #1 which is fully floating and because of SPICE failing to find a correct initial condition. You have therefore two solutions:

1) edit the graphics and unselect the option Initial DC Solution.
2) (much desirable) put the propety {PREFLUX=0} in each primary inductor L1:A, L2:A and L3:A

Be happy!

[understress]

Ettore,

Again, many thanks for the help. Unchecking the 'Initial DC solution' option solved the problem. Learning how to use a tool while under pressure to complete a design is not fun. I've ordered some books on SPICE, but finding the time to read them will be the next challenge.

Also, clearing the chart data and doing a tidy reduced the design file size from 1.9M to 1M. BUT, the zipped versions went from 686K to 27K! A huge difference.

Scott

[Ettore]

Ok. Most of the remaining 1M now depend substantially from the logo bitmap of your company in the header block which zip program is able to compress much efficiently as there are long sequence with same data. Of course, data into the simulation graphics are another story.

Yes, the initial DC condition option works although it applies for the whole circuit. If this affects (or it will) on the simulation performances in a future extension of your circuit then use the solution #2, which applies to transformer only.

[understress]

Ettore,

I have added PREFLUX=0 to the primary inductors of my transformer. If I uncheck 'Initial DC condition' for an analog graph, the SPICE simulation appears to run. The progress bar in the lower left counts from 0% to 100%. Some of the analog graphs I have will show data after the simulation, but some won't. If have the initial solution checked, then I get an error at the start of the simulation and it fails. The error is timestep too small. The node referenced depends on which graph I'm trying to simulate.

I have been able to intermittently been able get an error message of: Duplicate property 'IC' discrepancy in net COMMON. Had +0V and 0. I found a capacitor IC property (in a negative supply) that when removed makes this error go away. But removing this property doesn't change the ability to simulate.

I have attached my full design in hopes that maybe you will be able to find where my error lies.

Thanks,

Scott

[Ettore]

Yes, PREFLUX=0 is definitly the right way to go.

I cannot see particular error from your side.
The problem here is the floating secondaries and this creates any sort of simulation convergence issues which are quite difficult to fix out.

There are some points that is worth to comment:

1) The terminals SUPPLIES_+15V_LOGIC & SUPPLIES_-15V_LOGIC are power terminals. It means - from a simulation point of view - they behave like voltage generators. It is correct that you have configured them in the power rail but you should then exclude from simulation U1 and U3 regulators otherwise it is like connecting a 15V DC generator to the regulators output. To exclude a part from simulation edit the part itself and unselect the proper option.

2) In order to make the circuit converging much better I have made any effort to arrange the secondary windings reference and circuits such as they are referred to ground: SPICE does require ground as the reference. Primary is not so important and can be left floating - through a 2M resistor to ground, though. So, I have removed the net COMMON which you had configured in the power rail and have connected the suitable nodes to GND.

3) I have also increased the derivative capacitors of the TRIGGER circuits just to improve the strenght of the SCR gate signals. Probably is not what you wanted but I did that just to get a signal into the BRIDGE graphics in the last page.

4) The rectifier section (D1 to D6 and C1, C2 and regulators) in the root sheet #1 is (surprisingly) the main reason why you get simulation errors in your circuit. While I do think the circuit is correct, I believe it depends by something related with the transformer model, even though I cannot think to a different way to model a transformer with inductors. I have simulated separately this section and got it working although I have made the correct amplitute and phase signals with an alternative equivalent circuit not using the transformer. The file is enclosed in the attached zip file.

Anyway, the circuit is converging reasonably well at the present but is possible that convergence problems may still arise as you add other parts to simulate. A way to improve the convergence of your circuit is by replacing the actual transformer model with simple sine generators with the expected amplitudes and phases.

If you have further problems with your design then you may PM or e-mail me.
I will try to help you in my spare time as all of this is going to become a little off the purpose of our software support.