Labcenter Community Support Forums

OK, I think I have sorted it - I have added an "&" to the BSDL end of line script, for the GND pin numbers. This makes sure that that the GND pin pin-numbers are now loaded, I guess. Now I get GND{00} etc pins in the "Package Device" stage. No, I have gone back to the "P...

Thanks Ettore, When I read the pin information in from the BSDL script, all the pins including the GND pins seem to be recognised in the Make Device utility : However when one progresses to the next stage, the VCC pins are included (as per VCC{00}) but the GND pins are not, see previous diagram. I a...

Hi, I am importing a BSDL pin script for an Altera 256 pin FPGA. The BSDL script has been modified to contain CLK, VCC and GND references. At the Make Package stage, the VCC pins are all listed thus : VCC{00} VCC{01} VCC{02} ...... The GND pins are not listed. When the correct BGA package is attache...

Thank you for the BSDL import feature in Schematic Capture : Library => Import BSDL This offers a very nice way of generating packaging pinouts from manufacturers' BSDL files. (An earlier discussion on generating them from spreadsheet data is at : http://support.labcenter.co.uk/forums/viewtopic.php?...

Oh I do thank you so much David.
That looks good.
I have been working in a range of very different domains recently, and I think sometimes it wipes things I once knew - or makes them slow to find.
Really appreciated.
cheers,
Beau

Hi, I feel a bit silly, I have a number of boards that do what I am trying to do now, but it is over a year since I have laid out a PCB : I am trying to connect some pins on an IC to a board IO connector, via a bus. It all looks OK but on the PCB those connection are missing. I have on Root sheet 1 ...

I am having problems connecting power supplies when sub-circuits are being used. The problem comes when I have a (repeated) sub-circuit that outputs +1.8V, and are internally named "+1.8V". Now firstly I would expect to find a sub-circuit "power output" pin; the "power"...

OK, I found an answer to my problem of Edit => Replicate apparently doing nothing : In the help files on "Make Package" there is an example which uses Replicate, which has units (mm) in the offset. I have successfully run Replicate now, inserting a sufficiently large Y offset (giving the u...

Hmm, Thanks for this, it is exactly what I need right now. I can get the ISIS sub-circuit part to work, ending up with 2 circuits : 1st with U100, U101 ... , 2nd with U200, U201 ....; etc. However when I go to Ares and select all the layout for one sub-circuit (it all highlights), go to "Edit&q...

OK,
they say it is OK if I say use "Mech2" for the outline - that works OK.
cheers,
Beau

Hi, I am sending some designs for pcb etching, where a number will be combined on one panel, I am requested to also send the board outlines in their own Gerber files. When I try to do this I just get a file .....- CADCAM READ-ME.TXT, with design info, but not a Gerber outline. Any ideas how I might ...

Thanks indeed David, that has worked a treat. Nifty video thanks. Now well on the way to having the power rails and their decoupling sorted. Using 2 newly defined padstacks : (Top-1-Bottom) (Top-14-Bottom) for this makes life very easy - thanks. cheers, Beau PS question : If a pad stack is 40-25, sh...

Yes on this layer I have two separate sets of thick traces feeding two different power rails from the connectors, to components on the top of the board.
Is this a problem given my Pro level 0 licence ?
cheers,
Beau

Thought I was using a via between top copper and copper on 14.
I do not know what a padstack is : is it something like a set of pads : top, 14, bottom ?
If this is legal it would be very useful.
Have not had/used multi-layer software before.
cheers,
Beau

Hi, I have a thick inner power trace (layer 14) that is failing to connect to either the (AVDD) pins on a connector or the (AVDD) pins on vias that are set to go from top copper to layer 14. Anyone have any idea what I am doing wrong ? cheers, Dr. Beau Webber bad-connection.jpg This is with AVDD hig...