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Hello, I have a question for you. The Schematic circuit including the LED '7SEG-MPX2-CA-BLUE' can display the result i want.Namely,the circuit can work normally .But when it is debuged by ASF.There will be an error message as shown below: 'ERROR: [L2] LEDMPX.DLL failed to create DSIM model for primi...

I know what you said, and i will try again to prove it. Thank you for your reply.
have a goodday!!

hello:
i have a question recently. what's the limit of the clock frequency of the mcu 8051 in simulation .
otherwise. use proteus to simulating,how high the clock frequency can supply.

hello,
Recently,i have some questions about the gerber output of the ARES.
1.what's the difference of the format of gerber between proteus and protel. proteus is .txt and protel is .cam.
2.the gerber output of proteus can be opened by protel?how to do it.

Hi,Please see the attached design,how to explain the action of ULN2003A?
I found it need a pullup resistor to get right output.

It works well in VSM demo SP4,but fail to do so with professinal version. Somthing more,that I find I can't use some debug operation (step in,step over) with the source code window in Proteus 6.9 SP4 professinal.

When I update Proteus to SP4,everytime when I debug in Keil and simulate in Proteus,it report"Error: Target DLL has been cancelled...."
What's wrong?

:)Thank you! Now I know how to solve the problem,would you like to
tell me something more about the reason of it?

This DSN is located at "Motor Examples" sub-directory". When I simulate this design, Proteus show the following message: [SPICE] DELMIN increased to 8.88178e-16 due to lack of time precision [SPICE] Error 106 - TRAN: Timestep too small; time = 4, timestep = 3.46193e-16: trouble with U...

My design is using LPC2104 and the IDE is ADSv1.2, I want to watch C source code in Proteus. Iain said that Proteus need ELF/DWARF format output ,I use ADS's Codewarrior to output an ELF file, but simulation failed when I load this ELF. “PROSPICE - Internal Exception: divide by zero in module 'LOADE...

what's the meaning of " (use .elf - make sure dwarf file exists in same directory)"?
I try to output .elf file,but simulation failed when I used this file:

Internal Exception:divide by zero in module "LOADER.DLL"

I find the C source code can be displayed during simulation paused to step in Tiny Chess of 87c51, but I can't make my C code to display in my design, I'm using Keil uV2.
What to do so as to watch C51 source code directly in Proteus?

Using the TERMECHO sample design,I try to connect COMPIM to a real board based on 89c51 @9600bps.
First I got nothing from the virtual terminal,and,my ISIS had no response when I stopped simulation.
What's wrong with my operation?
My board works well when connect directly to PC.

I test COMPIM by VSPD virtual serial port software,I find the baudrate setting has nothing to do with the result, data is always transfered well .
why?

Another approach is to use ASCII Data Import in ISIS to build a translation table for the packages you use. You can then apply this to any ISIS schematic prior to netlist generation and the netlist will contain the translated packages. The script would look something like this: DATA PACKAGE : PACKA...