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While running a long simulation, over half an hour or sometimes more, when a break point is hit (e.g. logic contention) it would be very useful to be able to rewind the simulation to a point just before the logic contention happens and proceed to single step. It would be useful to be able to repeat ...

Yes, except one of the jobs of the simulation side of the software is to aid in designing working hardware. It's why the ICs have simulated propagation delays etc. However is this case, the fact the simulation software does not "have the possibility to emulate the effects of the interference on...

The issue here is not the timing of the tri-state values for a single IC, it's the issue that the simulation isn't allowing for the effects of interference on tri-state levels across the whole simulation, which weak pullups help to mitigate. In a perfect simulated world the 74ls273 will interpret a ...

It's a 74LS126 and the environment does have a lot of 12MHz+ signals from several hundred ICs in close proximity. So, what would be useful is if Proteus had the option to globally set and simulate all tri-state high impedance levels as if they were in such an environment. This means the simulation w...

I've recently been working on some 5V TTL designs and noticed a bug when the hardware was built. The original schematic has the output from 5F being routed through an optional tri-stated bus buffer U80 which then gets latched by 5H. The purpose of U80 being optionally tri-stated is to optionally for...

Thanks for that. The snippets and sub-circuit experimentation allowed me to work towards a good editing model. The primary instance of the reusable block is in schematic as normal, allowing for rapid iteration and simulation. Then I just copy and paste it into an empty sub circuit once and the rest ...

I've been working on a large complex design, but I've created this minimal example to show the issue. The simple design has a schematic, with an obviously identical functional block identified in bounding box in the schematic. It uses 5V TTL ICs and the only differences are the inputs and outputs. C...

Splendid, cheers

Created a small tool for filtering connectivity errors between boards: https://github.com/martinpiper/BombJack/blob/master/CheckConectivity/CheckConectivity.cpp It accepts: <IPC file> <pre-production check text file> [optional netlist names text file] It will output all unique netlists that do not h...

As part of the pre-production check, or connectivity check, it would be very useful if it can also list the net names that are missing or have not been routed. Exporting the missing connectivity information with net names to a plain text file would also help greatly. Ideally it would be great to hav...

Thank you both for the quick replies. Noted the coarser placement grid, it does help a lot. Interestingly, I noticed that starting the autoplacer without pressing the scheduling button still seems to schedule the bigger packages first. The component list will refresh and the vertical scrollbar will ...

With the attached project, starting the autoplacer with default options takes about 15 minutes to place all the boards. This seems rather slow.
CPU is consistently at 12%, indicating one core is fairly active but the others are idle.
Is this normal expected performance with this project?

While the existing Stackup Wizard is quite useful, I've noticed that if there are existing power planes then it doesn't seem to remove those. It would be great if there was a quick and easy option to clear all the planes, layer names and regenerate. Another improvement to the Stackup Wizard would be...

Yes, but note that once a : is used then the part after the component does not appear to be able to be edited or removed. Meaning that the component is stuck with a truncated identifier.

Reproduction: 1) Load the attached project New Project.pdsprj 2) Note parts U2:ARGHH U4 and U3:BLAH in the schematic 2) Tool->Global Annotator 3) Scope: Whole Design + Mode:Total + Initial Count: 1 4) Click OK 5) Note parts references have been truncated to: U3:A U2 U1:B in the schematic 6) Editing ...