Search found 43 matches
- Wed 2020-07-15 8:24
- Forum: PCB Layout
- Topic: Best practice for multiple boards in one project
- Replies: 8
- Views: 4709
Re: Best practice for multiple boards in one project
Thanks indeed Ian, That will be very useful. I have also been pointed to "Project Clips" as a way of saving boards, and then adding them as sub-boards. VIdeo : https://www.youtube.com/watch?v=zb2roIq1lzo This seems to work very well, I appear to be making good progress with a combined boar...
- Wed 2020-07-08 17:13
- Forum: PCB Layout
- Topic: Best practice for multiple boards in one project
- Replies: 8
- Views: 4709
Re: Best practice for multiple boards in one project
May I ask if there are any updates re etch & assemble for multiple designs on one PCB job ? From the above it does not really look practical, given the need for a pick and place file. Or have I mis-read ? I have a number of designs I need to print, some boards that are down to 12 mm x 24 mm in s...
- Tue 2018-08-14 13:02
- Forum: PCB Layout
- Topic: Partial power planes not connecting
- Replies: 1
- Views: 453
Partial power planes not connecting
HI, I am able to generate as many partial power planes as I like, but they are not connecting to the pins : This is with a +15V partial power plane. The left two pins are ground pins, and are correctly connecting to ground planes, but show no relief at the +15V power plane. The right two pins are sp...
- Wed 2017-11-01 18:29
- Forum: PCB Layout
- Topic: PADS chip pinout import ?
- Replies: 2
- Views: 443
Re: PADS chip pinout import ?
Hi Iain,
the problem seem to be the PADS version numbers.
Proteus is looking for a V9.5, the downloaded files are V9.0,
which 'Paul Woolford' of Samacsys,com believes is the most recent version.
If I try and read in : QFN50P500X500X100-33N.d
I get as below
cheers, Beau
the problem seem to be the PADS version numbers.
Proteus is looking for a V9.5, the downloaded files are V9.0,
which 'Paul Woolford' of Samacsys,com believes is the most recent version.
If I try and read in : QFN50P500X500X100-33N.d
I get as below
cheers, Beau
- Wed 2017-11-01 15:23
- Forum: PCB Layout
- Topic: Proteus & Library Loader
- Replies: 5
- Views: 1169
Re: Proteus & Library Loader
Thanks for both replies Iain,
I always seem to be designing with chips for which there is nothing in the libraries, this is becoming a significant issue for me now.
cheers, Beau
I always seem to be designing with chips for which there is nothing in the libraries, this is becoming a significant issue for me now.
cheers, Beau
- Wed 2017-11-01 14:21
- Forum: PCB Layout
- Topic: Proteus & Library Loader
- Replies: 5
- Views: 1169
Re: Proteus & Library Loader
Hi, Library Loader data is provided by RS Components and other distributors. It is supposed to be able to produce PADS output, which Proteus is supposed to be able to import. Has anyone been able to actually create a PADS file this way ? I get all the following windows / error messages : cheers, Bea...
- Wed 2017-11-01 11:56
- Forum: PCB Layout
- Topic: PADS chip pinout import ?
- Replies: 2
- Views: 443
PADS chip pinout import ?
Hi, I am trying to use the automatic data for chip pin and pad layouts, that RS and other suppliers now provide. After a range of error messages I now have the following files downloaded (for PADS I believe, which I understand Proteus can import) I recognise the .d and .p suffixes. But I have forgot...
- Sat 2017-10-07 13:20
- Forum: PCB Layout
- Topic: guard gap resist
- Replies: 6
- Views: 789
Re: guard gap resist
Thanks I see,
OK just doing it.
OK Done, all fine now, thanks.
OK just doing it.
OK Done, all fine now, thanks.
- Sat 2017-10-07 9:02
- Forum: PCB Layout
- Topic: guard gap resist
- Replies: 6
- Views: 789
Re: guard gap resist
I think this may be relevant to the problem I am having. I have just added a device with a tiny WDFN 6-Pin pad (taken from the Proteus package library) to a partially complete design. When I place it, It shows a large number of DRC errors, even if I reduce the menu Technology setting to 1th. The act...
- Thu 2017-10-05 8:41
- Forum: Schematic Capture
- Topic: How do I import a Netlist ?
- Replies: 0
- Views: 3504
How do I import a Netlist ?
Hi, I have a schematic for a partly built design created by a colleague (using DipTrace), and I want to try and complete the design in Proteus. DipTrace can export the Netlist in a range of formats. I see in the Forum : "You can then start ARES and import a netlist (if allowed by the version yo...
- Mon 2017-10-02 21:41
- Forum: Schematic Capture
- Topic: BOM Report Individual References
- Replies: 4
- Views: 4683
Re: BOM Report Individual References
Thanks, just what I was looking for, thanks !
Beau Webber
Beau Webber
- Fri 2017-03-31 16:39
- Forum: PCB Layout
- Topic: Connector pins fail to connect to ground plane.
- Replies: 3
- Views: 687
Re: Connector pins fail to connect to ground plane.
Yes that worked fine. All I had to do was right click on any pin on the connector, say edit pin, and that told me which pinstack it was using. Then go to the left menu of icons, and click on the pinstack icon. Choose the same pinstack from the list, edit, and copy the existing top and bottom entries...
- Thu 2017-03-30 15:24
- Forum: PCB Layout
- Topic: Connector pins fail to connect to ground plane.
- Replies: 3
- Views: 687
Re: Connector pins fail to connect to ground plane.
Thanks, I will give that a go.
cheers,
Beau
cheers,
Beau
- Thu 2017-03-30 12:34
- Forum: PCB Layout
- Topic: Connector pins fail to connect to ground plane.
- Replies: 3
- Views: 687
Connector pins fail to connect to ground plane.
Hi, I have a multi-pin connector where the pins that should be connected to ground fail to connect to the ground plane. I have had similar ground problems before, but this is not a bus-related problem. A wire from ground to the connector pin fails to connect with the ground plane, even when explicit...
- Thu 2016-11-17 22:13
- Forum: Schematic Capture
- Topic: I am having trouble connecting to GND pins on a FPGA
- Replies: 4
- Views: 964
Re: I am having trouble connecting to GND pins on a FPGA
Here it now is a the Package Device stage, with the GND pins registering correctly, and all the pins correctly connected